Develop FPGA applications the way software is built.
Assemble tested, reusable packages instead of rebuilding the foundations for every project. Livt generates standard VHDL for the vendor tools you already use.
AI writes code. Livt gives it a workflow.
Every step up in abstraction lets a team handle more complexity. Tools that only generate VHDL help at the bottom level. Livt provides the levels above it.
- AI-assisted developmentFaster iteration within a verifiable workflow
- Platform and automationRepeatable builds and validation
- Frameworks and packagesLess repeated work through reuse
- Structured codeClearer components and testable behavior
- Low-level HDLDirect hardware description
More productive development. Quality supported by reuse, testing, and repeatable workflows.
AI-to-VHDL solves code generation. Livt solves the workflow around code generation.
Livt brings these layers together—from reusable foundations to AI-assisted development.
Real designs, built with AI assistance and Livt.
A live camera on an LED panel, and over Ethernet.
A camera feeds a Livt design on an Arty A7-100T. The picture is processed in FPGA logic and shown live on a 128×128 LED panel, while the same video streams to a PC over Ethernet.
- Capture, filters, networking and display driver are reusable Livt packages.
- Tested in simulation, then generated as VHDL for a standard Vivado project.
- Timing-clean implementation on the board.
Built with
A web server with a different attack surface.
Ethernet, TCP and HTTP run as FPGA logic and the pages are stored as data. With no CPU and no call stack behind HTTP handling, classic code injection has no comparable mechanism to target.
- Behaviour lives in logic and content in memory, each with its own lifecycle.
- A different execution boundary, not automatic security: parser bugs and denial of service still need review.
- Demo scope: three GET routes, one peer, no TLS.
Built with
Try it yourself: web application · Arty A7-100T board project
Encrypted files from a USB stick, handled in logic.
A USB host, a FAT32 reader and authenticated decryption, all written in Livt. Files stream from a stick through the FPGA, and data is trusted only after its authentication tag has been verified.
- USB host and file system run as FPGA logic, controlled from a UART command line.
- Cryptographic building blocks come from a reusable package.
- Tested in simulation before it runs on the board.
Built with
From code to FPGA in four steps.
Components you compose instead of rewrite.
Ready-made packages for networking, USB, buses, I/O, math and more. Explore the Livt.* base library and further reusable packages in the package catalog.
Fits into the flow you already have.
Livt does not ask you to replace your tools or rewrite your existing IP. It adds a higher-level way to describe new hardware on top of the flow you trust.
- Generated VHDL is readable and synthesizable, so vendor flows, constraints and reviews stay as they are.
- Handwritten HDL and HLS blocks can be used next to Livt components through clear interfaces.
- Experienced FPGA engineers keep explicit control of clocks, timing and resources.
Try Livt on your own design.
Create an Eccelerators account to receive your licence, install the extension for Visual Studio Code, and build your first design.