FPGA & ASIC language

Livt

Write expressive hardware designs, generate production-ready VHDL, and test your logic with a fast, modern development workflow.

Designed for Hardware

A language whose execution model matches how FPGAs work.

Many languages that target FPGAs today were designed for CPUs — with a sequential, stack-based model — and then adapted to hardware synthesis. That mismatch leads to hidden inefficiencies, restricted language subsets, and results that are hard to predict or inspect. Livt takes a different approach: its execution model was built around hardware concurrency and dataflow from the start, so there is no mismatch to paper over.

  • The language model reflects hardware concurrency rather than imposing a CPU execution model.
  • Concise syntax reduces the gap between design intent and code without sacrificing precision.
  • The compiler applies domain expertise to generate functionally correct VHDL.
  • Common HDL pitfalls are caught at compile time rather than in simulation.
  • Generated VHDL is human-readable and integrates with existing toolchains.
In the docs
Behavior-first design
Livt execution model
Testing

Test your hardware logic the way software engineers test code.

Livt has a built-in test framework so verification is a natural part of the development workflow — not a separate effort requiring manual testbench authoring. Every component can have tests, and the simulator runs them with a single command.

For hardware engineers

  • Write test components alongside design components in the same project.
  • No manual VHDL testbench boilerplate required.
  • Simulation output is readable and clearly reports pass or failure.
  • The write–build–test loop gives rapid feedback during development.

For software engineers new to FPGAs

  • Familiar test patterns — annotate a component with @Test and write test functions.
  • Run all tests with livt test, just like a unit test framework.
  • Simulation results appear in the terminal with timestamps and messages.
In the docs
Unit Tests
Example 
component LoopbackUartTest
{
    uart: LoopbackUart

    new()
    {
        uart = new LoopbackUart()
    }

    @Test
    fn TestLoopbackPattern()
    {
        uart.Transmit(0xAA)

        Simulation.Wait(LoopbackUart.TICKS_PER_BIT * 12)

        assert uart.IsDataAvailable() == 0b1
        var received = uart.Receive()
        assert received == 0xAA
    }
}
1 2 3 4
  1. 1 Verification code stays close to the hardware logic it tests.
  2. 2 Setup stays explicit, with the loopback instance created in the constructor.
  3. 3 The test drives a real UART bit pattern into the loopback path.
  4. 4 Assertions make the expected receive behavior easy to verify.
Hardware-Software Integration

Processor-to-FPGA interaction built into the language.

HxS — Eccelerators' register interface generator — is integrated directly into Livt. That means defining the register interface between a processor and your FPGA design, generating the HDL, and generating the software access layer are all part of the same Livt workflow. There is no separate tool invocation, no format mismatch, and no manual synchronization between the hardware and software sides.

What this means in practice

  • Define CPU-visible registers, blocks, and bus-level interface details directly from your Livt project.
  • Generate VHDL register interfaces and software access code from the same interface description.
  • Hardware and software teams work from a single source of truth rather than maintaining separate, diverging specs.
  • Supported bus types include AXI4-Lite, Avalon, and Wishbone.
  • Software access layers are generated for C/C++, Python 3, and Rust.
In the docs
Learn about HxS
Example 
using Livt.IO
using Livt.HxS

@Interface(BusType="AXI4Lite")
component Controller
{
    uart: Uart

    new(rx: in logic, tx: out logic)
    {
        uart = new Uart(rx, tx)
    }

    @Register(Id="StatusRegister")
    @Data
    fn SendStatusReport()
    {
        uart.Send("System ready".Encode())
    }
}
1 2 3
  1. 1 The Livt.HxS import brings the HxS annotations into scope.
  2. 2 The @Interface annotation sets AXI4Lite as the bus type.
  3. 3 @Register and @Data define a writable register element that lets the processor trigger SendStatusReport().
Tooling and Ecosystem

A growing ecosystem built for modern engineering workflows.

Livt is more than a language — it is the foundation for a toolchain that brings FPGA and ASIC development in line with modern software practices. Built-in package management, IDE integrations, and CI/CD support are part of the plan from the start.

  • Package management is provided out of the box, as a core part of the toolchain.
  • A comprehensive base library with ready-to-use components and utilities.
  • AI and LLM-assisted tooling for intelligent completion and guided learning.
  • Frameworks for signal processing, communication protocols, and hardware-software interfaces.
In the docs
Get started with Livt
Livt ecosystem