Language introduction

Introduction

Livt brings modern software engineering practices to FPGA and ASIC development — expressive syntax, robust tooling, and a productive write–build–test loop.

FPGA and ASIC development has traditionally relied on hardware description languages such as VHDL or Verilog. These languages, while powerful and precise, demand a level of verbosity and low-level detail that can slow down development, hinder maintainability, and create steep learning curves for new developers. Modern software engineering, on the other hand, benefits from high-level languages, expressive syntax, robust tooling, and well-established design methodologies — advantages that have yet to be fully embraced in the hardware design world.

The Origin Story of Livt

Livt was born out of frustration with the complexity of traditional HDL-based development. Over the past decades, software engineering evolved dramatically — rich IDEs, package managers, testing frameworks, continuous integration, and a wide range of tools help developers manage complexity and maintain high-quality codebases. FPGA development, by comparison, changed very little — workflows remain cumbersome, tool integration is minimal, and the languages themselves offer limited abstraction or automation.

This gap created a drift between the software and hardware worlds. For software developers, FPGA design can feel like stepping back in time. For hardware engineers, the lack of modern practices often means more time spent on syntax and tool quirks than on a design's behavior.

Livt aims to close that gap.

Who Livt Is For

  • Hardware engineers who want to work at a higher abstraction level while maintaining the precision and reliability of VHDL.
  • Software engineers — especially microcontroller developers — who sometimes need to work with FPGAs or ASICs and prefer a modern programming environment.

By meeting both groups halfway, Livt provides a language that is approachable, powerful, and deeply integrated with FPGA workflows.

Behavior First, Details Later

A core principle of Livt is to design behavior first and let the compiler translate it into high-quality HDL. Instead of getting lost in signal declarations, clock handling, and process blocks, you focus on what the design should do. The Livt compiler applies built-in domain expertise to generate human-readable, functionally correct VHDL, catching common pitfalls early and integrating seamlessly with existing FPGA toolchains.

Looking Ahead

Livt is the foundation for a growing ecosystem:

  • A rich package library covering common hardware design needs
  • A comprehensive base library with ready-to-use components and utilities
  • Frameworks for domains like signal processing, communication protocols, and hardware-software interfaces
  • AI and LLM-assisted tooling for intelligent completion, boilerplate reduction, and guided learning

The vision is to make FPGA and ASIC development faster, more reliable, and genuinely enjoyable — where modern software practices and hardware design finally meet.

A First Taste: Hello World in Livt

Create a new project:

bash 
$ livt new HelloWorld
$ tree HelloWorld

Project structure:

bash 
HelloWorld/
├── livt.toml
├── src
│   └── MyComponent.lvt
└── tests
    └── MyComponentTest.lvt

Application logic:

livt 
namespace Livt.App

component MyComponent
{
    public fn SayHelloWorld()
    {
        Simulation.Report("Hello World!")
    }
}

Built-in test:

livt 
namespace Livt.App.Tests

using Livt.App

@Test
component MyComponentTest
{
    my_component : MyComponent

    new()
    {
        this.my_component = new MyComponent()
    }

    @Test
    fn TestSayHelloWorld()
    {
        this.my_component.SayHelloWorld()
    }
}

Building the Project

bash 
$ cd HelloWorld
$ livt build    
Using extension VHDL v0.0.0-0000000 for compilation.
Using extension HxS v0.0.0-0000000 for compilation.
Compiling Livt.HxS.lvt
Compiling Livt.Lang.Annotations.lvt
Compiling Livt.Lang.Types.lvt
Compiling Livt.Lang.lvt
Compiling Livt.Simulation.lvt
Compiling MyComponent.lvt
Compiling MyComponentTest.lvt

The build produces a clean, human-readable VHDL output directory ready for synthesis.

Running the Simulation

bash 
$ livt test    
Nothing to compile - all components are up to date.
analyze .../src-gen/debug/main/Livt.App.MyComponent.Package.vhd
analyze .../src-gen/debug/lib/Livt.Lang.TestContextProvider.Package.vhd
analyze .../src-gen/debug/tests/Livt.App.Tests.MyComponentTest.Package.vhd
analyze .../src-gen/debug/lib/Livt.Lang.IContext.Package.vhd
analyze .../src-gen/debug/lib/Livt.Lang.IComponent.Package.vhd
analyze .../src-gen/debug/lib/Livt.Lang.ITestComponent.Package.vhd
analyze .../src-gen/debug/lib/Livt.Lang.TestContextProvider.vhd
analyze .../src-gen/debug/main/Livt.App.MyComponent.vhd
analyze .../src-gen/debug/tests/Livt.App.Tests.MyComponentTest.vhd
elaborate mycomponenttest
.../Livt.App.MyComponent.vhd:58:41:@165ns:(report note): Hello World!
.../Livt.App.Tests.MyComponentTest.vhd:198:41:@275ns:(report note): Simulation finished

The simulator confirms the expected message and shows the simulation lifecycle. Even for this simple case, Livt removes the need for verbose manual testbenches and enables a quick write–build–test loop.

In the chapters that follow, we will explore the building blocks of Livt, walk through its syntax and semantics, and demonstrate how it enables a modern, productive, and reliable workflow for FPGA and ASIC design.