HxS Release Notes

HxS 1.0.20 is a focused bug-fix release for generated VHDL register interfaces. It corrects read-pulse generation for externally acknowledged registers and ensures configured bus timeouts are retained by generated IP-XACT wrappers.

Correct Read Pulses for Externally Acknowledged Registers

Synchronous externally acknowledged read-function registers now generate the expected read pulse with Avalon and Wishbone. The AXI4-Lite generator also correctly handles read pulses for externally acknowledged registers, keeping generated behavior consistent across the supported bus interfaces.

Preserve Bus Timeouts in IP-XACT Wrappers

Generated IP-XACT wrappers now forward the configured bus timeout instead of dropping it, so the wrapper honors the timeout setting from the original design.

HxS 1.0.20 is available from the downloads section.

HxS 1.0.19 is a focused correctness release for generated VHDL register interfaces. It resolves a naming inconsistency that could appear when an interface used interface-scoped signal names.

Consistent VHDL Output Naming

HxS correctly declared writable output ports with both their register and field names, but the final assignment could omit the register prefix. For example, a port declared as control_enable could be assigned through the non-existent target enable, causing the generated VHDL to fail compilation and requiring a manual correction.

-- HxS 1.0.19 keeps the declared port name and assignment aligned
control_enable <= wreg_enable;
control_duty_cycle <= wreg_duty_cycle;

Output assignments now follow the same naming scope as their port declarations. Register-qualified ports therefore retain their register prefix throughout the generated design, producing self-consistent VHDL that compiles without post-generation edits. Regression coverage protects this behavior across the supported Avalon, AXI4-Lite, and Wishbone interface variants.

HxS 1.0.19 is available from the downloads section.

HxS 1.0.18 is a focused quality release for teams building and maintaining hardware/software register interfaces. It improves naming consistency, broadens bus-size support, and makes project results easier to review across common bus configurations.

More Predictable Register Naming

Register-scoped naming is now more consistent for projects that prefer explicit register prefixes. When register naming scope is enabled, fields keep the register prefix even in simple single-reference cases. This makes naming conventions easier to apply across small interfaces and larger register maps alike.

Clearer Reset Defaults

Reset default names now stay aligned with their register context. This helps avoid ambiguous names in interfaces that reuse similar field names across multiple registers, and it makes review of large interface descriptions more predictable.

Improved Bus Interface Support

Avalon users now get response-signal support throughout the HxS flow. The release also strengthens 64-bit and 128-bit bus access for Avalon, AXI4-Lite, and Wishbone configurations, including wider read and write checks.

Updated Verification Environment

The verification projects were refreshed for SimStm 2.0.4 and expanded with bus-size checks, including a 128-bit access test. This gives teams better confidence when using wider bus widths in production interfaces.

HxS 1.0.18 is available from the downloads section.

Get ready to explore the latest release of HxS, version 1.0.17! Download it now and uncover a host of enhancements and bug fixes that promise an even smoother experience.

• Added Treat Warnings as Errors Compiler Flag
• Asynchronous BitBehaviour.Transparent and BitBehaviour.WriteTransparent
• Support Byte-wise Bus Access
• Fixed Overlapping Registers
• Fixed Asynchronous Bus Reset Initialization
• Fixed Parameter Syntax Validation
• Eclipse Plugin and VS Code Extension

Added Treat Warnings as Errors Compiler Flag

In this release, we have added the compiler option --treat-warnings-as-errors or in short -t. When this option is activated, all warnings are treated as errors. You can apply it as follows:

hxsc -t -o src-gen vhdl MyRegisterInterface.hxs

Asynchronous BitBehaviour.Transparent and BitBehaviour.WriteTransparent

As of now, it is permitted to use bit fields with BitBehaviour.Transparent or BitBehaviour.WriteTransparent together with asynchronous registers. Notably, even when the bit behaviour is set to transparent, the write cycle will be registered to ensure that the data reaches its block.

register MyRegister
{
    Async = true;
    Bits = [MyData];
    
    data MyData
    {
        BitBehaviour = BitBehaviour.Transparent;
    }
}

Support Byte-wise Bus Access

Until now, accessing the bus was constrained to addresses that were multiples of 4. With this release, all three bus interfaces — Avalon, AXI4-Lite, and Wishbone — now support byte-wise bus access.

Fixed Overlapping Registers

We encountered an issue with our automatic register address calculation. When there were, for example, three registers containing only a few bits each, they were incorrectly assigned to the same address. In the following example, MyRegister0, MyRegister1, and MyRegister2 would all have been assigned to address 0x0.

block MyBlock
{
    Registers = [
        MyRegister0,
        MyRegister1,
        MyRegister2
    ];

    register MyRegister0
    {
        Width = 3;
    }
    
    register MyRegister1
    {
        Width = 9;
    }
    
    register MyRegister2
    {
        Width = 8;
    }
}

This behavior was counter-intuitive and has been fixed. Now, registers are padded to the next byte boundary, ensuring that each subsequent register starts at the next available address. For example, with the registers mentioned above, MyRegister0 starts at 0x0, MyRegister1 starts at 0x1, and MyRegister2 starts at 0x3.

Fixed Asynchronous Bus Reset Initialization

We previously missed initializing signals in the asynchronous domain, resulting in undefined signals during simulation. This issue has been addressed. Now, all signals are properly initialized and set to specific values.

Fixed Parameter Syntax Validation

There was an error in the validation process of the parameter syntax used to override properties of existing HxS objects, such as the register in the following example. This validation error prevented the overriding of properties like the Bits property, which expects lists.

block MyBlock
{
    Registers = [
        MyRegister(Bits=[MyData0]),
        MyRegister(Bits=[MyData1])
    ];

    register MyRegister {}

    data MyData0
    {
        Width = 8;
    }
    
    data MyData1
    {
        Width = 24;
    }
}

This issue has been fixed, and the parameter syntax can now be used to override lists as well.

Eclipse Plugin and VS Code Extension

With every release, we ensure the HxS Eclipse plugin and VS Code extension are up-to-date. You can find both IDE integrations ready for download here.

Great news for HxS developers: We are releasing version 1.0.16. In our ongoing commitment to security, we regularly maintain and update our dependencies. With this release, we are ensuring a robust and secure user experience. Please be aware that starting from this release, Java 17 or higher is a requirement.

In addition, we have dedicated efforts to enhance VHDL code integrity, systematically addressing syntax issues of the generated files. HxS 1.0.16 is now available in our download section.

Exciting news for HxS users: version 1.0.15 is here! This release focuses on improving VHDL code integrity, effectively fixing syntax issues across various HxS configurations. Explore these improvements — HxS 1.0.15 is now ready for you in our download section.

We are excited to unveil the newest iteration of HxS. This release brings enhancements to VHDL code's quality, addressing and fixing potential syntax errors in various HxS code configurations. Experience the improvements firsthand — HxS 1.0.14 is now available in our download section.

Get ready to explore the latest release of HxS, version 1.0.13! Download it now and uncover a host of enhancements and bug fixes that promise an even smoother experience.

• References and Scope Enhancements
• Set Default Data Bus Width to 32
• Auto-Calculation of Address Bus Width
• Derive Alignment from Data Bus Width
• Fixed Asynchronous Read-Only / Write-Only Register Bug
• Eclipse Plugin and VS Code Extension

References and Scope Enhancements

Now, you can refer to objects from the same or outer scopes without the need for their fully qualified names. When looking up a reference, the first object found is used, starting from the reference's scope and going up to the outer scope.

interface MyInterface
{
    block MyBlock
    {
        Registers = [MyRegister];

        register MyRegister {} // Hides MyRegister of outer scope
    }

    register MyRegister {} // Is hidden for MyBlock.Registers
}

This makes the code cleaner and more concise, as it is possible to reference objects directly without specifying their full paths each time.

Set Default Data Bus Width to 32

In this update, we have introduced a breaking change by transitioning the default data bus width from 8 to 32 bits. This modification may require adjustments in existing HxS descriptions.

interface MyInterface
{
    DataBusWidth = 32; // Defaults to 32-bits and can be left out
}

Auto-Calculation of Address Bus Width

In our continuous pursuit of user comfort, we have introduced an automated calculation for the Interface.AddressBusWidth property. Now, if no specific value is provided, it derives the value from the blocks, eliminating the need for manual adjustments.

interface MyInterface
{
    AddressBusWidth = 8; // Is calculated and can be left out
}

Derive Alignment from Data Bus Width

The Alignment property of the Block object now determines the address alignment of contiguous registers in bytes by deriving its value from the DataBusWidth property of the associated Interface object. Given the default DataBusWidth of 32-bits, the alignment's default value is set to 4 bytes.

interface MyInterface
{
    DataBusWidth = 32;
}

block MyBlock
{
    Alignment = 4; // Is calculated and can be left out
    Registers = [
        MyRegister0,
        MyRegister1,
        MyRegister2
    ]
}

Fixed Asynchronous Read-Only / Write-Only Register Bug

Previously, defining a register as asynchronous with exclusively readable or writable bit fields could inadvertently trigger the generation of corresponding read or write parts using properties like ReadAckDelay or WriteAckDelay. This resulted in incorrect register interface behavior. We've addressed this issue, ensuring proper functionality, and now provide clear information that such properties have no effect and will be ignored.

register MyRegister
{
    Async = true;
    ReadAckDelay = 3;
    WriteAckDelay = 3; // Ignored
    Bits = [MyData];
}

data MyData
{
    Width = 32;
    Behaviour = BitBehaviour.Constant;
}

Eclipse Plugin and VS Code Extension

With every release, we ensure the HxS Eclipse plugin and VS Code extension are up-to-date. You can find both IDE integrations ready for download here.

We are excited to unveil HxS 1.0.12. It is now available for download. Discover a range of exciting new features such as AXI4-Lite support and improvements for IP-XACT.

• AXI4-Lite
• IP-XACT VHDL Wrapper
• Bus Reset Objects
• SPI Controller Example
• Eclipse Plugin and VS Code Extension

AXI4-Lite

After months of development and verification we added our third bus interface AXI4-Lite. Setting the BusType property of an interface to BusType.AXI4Lite is enough to create an AXI4-Lite register interface.

interface MyInterface
{
    BusType = BusType.AXI4Lite;
}

IP-XACT VHDL Wrapper

We always strive to reduce complexity and to keep tedious work away from developers. Therefore, we introduced the vhdl.ipxact.wrapper annotation. It instructs the VHDL generater to create a VHDL entity without any records for use by IP-XACT. The annotation is part of an interface object and can be used as follows.

interface MyInterface
{
    @Generator('vhdl.ipxact.wrapper', 'true')
}

Bus Reset Objects

We added the following bus reset objects to the HxS Base Library:

• BusReset.None - Bit field is not affected by bus reset
• BusReset.Sync - Bit field is affected by synchronous bus reset
• BusReset.Async - Bit field is affected by asynchronous bus reset

data MyData
{
    Width = 4;
    Resets = [
        BusReset.None,
        MySoftReset0,
        MySoftReset1
    ];
}

The dictionary syntax can be used as well. It enhances the readability if multiple resets are defined. Here is an example:

data MyData
{
    Width = 4;
    Resets = {
        0xU : BusReset.None,
        0x5 : MySoftReset0,
        0xF : MySoftReset1
    };
}

Further information about the reset behaviour can be found in the documentation of the data and enum objects.

SPI Controller Example

We continuously add practical examples to our the publicly available repository at GitHub. This time we added a SPI controller example, which shows advanced features of HxS.

Eclipse Plugin and VS Code Extension

We update the HxS Eclipse plugin and VS Code extension with each release. Both IDE integrations are available at the download section.

Great news! HxS 1.0.11 is now available for download. Discover a range of exciting new features and improvements.

• Added IP-XACT Extension
• Added Annotation for Identifier Customization
• Added Example Projects on GitHub
• Fixed Synchronous Registers with Asynchronous Properties

Added IP-XACT Extension

In order to improve our efforts for making HxS even more useful we added the IP-XACT extension. It can be used as follows:

hxsc -o src-gen ipxact src/MyInterface.hxs

The IP-XACT extension supports the standards spirit._1685_2009, and accellera._1685_2014. By default, the extension generates IP-XACT files compliant to the accellera._1685_2014 standard. It can be changed using an annotation for the interface.

interface MyInterface
{
    @Generator('ipxact.standard', 'spirit._1685_2009')
}

We are eager to improve the IP-XACT extension with each future release, so if you have any ideas how we might improve let us know.

Added Annotation for Identifier Customization

The VHDL, Python and C generators support the {vhdl, python, c}.naming.scope annotation to influence the creation of identifers. By default, generators create identifiers that are unique and short in length. Depending on the use case, it might be necessary to customize the creation of identifers. The annotation can be used as follows:

interface MyInterface
{
    @Generator('vhdl.naming.scope', 'interface')
    Blocks = [MyBlock];
}

block MyBlock
{
    Registers = [MyRegister];
}

register MyRegister
{
    Bits = [MyData];
}

data MyData
{
    Width = 8;
}

The example above will create the following identifiers for the VHDL package. The parts that are bold are influenced by the annotation.

    constant MYINTERFACE_MYBLOCK_BASE_ADDRESS : std_logic_vector(31 downto 0) := x"00000000";
    constant MYINTERFACE_MYBLOCK_SIZE : std_logic_vector(31 downto 0) := x"00000001";

    constant MYINTERFACE_MYBLOCK_MYREGISTER_WIDTH : integer := 8;
    constant MYINTERFACE_MYBLOCK_MYREGISTER_ADDRESS : std_logic_vector(31 downto 0) := std_logic_vector(x"00000000" + unsigned(MYINTERFACE_MYBLOCK_BASE_ADDRESS));

    constant MYINTERFACE_MYBLOCK_MYREGISTER_MYDATA_MASK : std_logic_vector(7 downto 0) := x"FF";
                

Using the interface scope will create the longest identifers, but ensures uniqueness. Further details and examples can be found in the documentation.

Example Projects on GitHub

We continuously work on repositories on GitHub offering practical examples.

• Interrupt Controller
• SPI Controller
• Double Buffer Controller
• Event Catcher

Fixed Synchronous Registers with Asynchronous Properties

If a register has been defined as synchronous, but has asynchronous properties like AsyncClk, AsyncRst, ReadAckDelay or WriteAckDelay, the generator has not ignored them. This lead to invalid VHDL code and has been fixed in this release. In addition, a warning is shown in case a register mixes synchronous and asynchronous properties.

register MyRegister
{
    Async = false; // Default value
    AsyncClk = "MyAsyncClkSignalName"; // Is ignored, because Async = false
    AsyncRst = "MyAsyncRstSignalName"; // Is ignored, because Async = false
    ReadAckDelay = 3; // Is ignored, because Async = false
    WriteAckDelay = 3; // Is ignored, because Async = false
}