Eccelerators.RiscV

Composable RISC-V processors for FPGA applications written in Livt. Start with a named core, or construct an engine and its providers explicitly. Both approaches use the same reusable components; resource choices are compile-time parameters.

Version 0.3.0 removes the scheduled reference layer and uses separate instruction-fetch and load/store ports with a system-level composition, retaining the sequential and pipeline core presets. See the release notes for migration guidance.

Choose a core

All presets are in Eccelerators.RiscV.Presets and borrow separate instruction and data providers implementing flip IRv32FetchPort and flip IRv32LoadStorePort, respectively.

The sequential engine favors a compact implementation. The pipeline overlaps fetch, decode/read, execution and commit. Both use synchronous register files; REGISTER_FILE_STYLE defaults to MemoryStyle.Block. The non-machine Zmmul presets and the pipeline machine preset also accept DSP_MULTIPLY, defaulting to iterative multiplication. The sequential machine preset uses the iterative multiplier; use explicit composition for a sequential DSP machine.

For example, these constructor fragments select a base sequential core or a machine pipeline with DSP multiplication:

core = new Rv32iSequentialCore(instructions, data)

core = new Rv32iZmmulPipelineMachineCore<0, MemoryStyle.Block, true>(instructions, data)

The application owns memories, firmware provisioning, peripherals and clock/reset. See core selection and integration before wiring providers or controls.

Compose a system

RvMemorySystem<Rv32iSequentialCore> owns a default 4 KiB fetch ROM and 4 KiB data RAM. For a custom address map, construct RvSystem<TCORE>(fetch, loadStore) with your own providers. Rv32FetchBus and Rv32LoadStoreBus route independent address windows; RvUartDevice adapts a buffered UART to load/store registers. See system composition for ownership, provisioning and interrupt wiring.

Use the package

Add the release under [dependencies] in your application's livt.toml:

[dependencies]
"Eccelerators.RiscV" = "0.3.0"

For development against a local checkout, use this dependency instead:

[dependencies]
"Eccelerators.RiscV" = { path = "../eccelerators-riscv" }

Run livt sync to resolve dependencies. The package uses Livt.IO 1.8.1 for memory storage and the buffered UART adapter.

Software targets are rv32i, rv32i_zmmul, or rv32i_zmmul_zicsr, with the ilp32 ABI, according to the selected core. Zmmul includes multiplication but not division. Machine cores implement a documented machine-mode subset with MRET, direct traps, timer and external interrupts. Compressed instructions, atomics, floating point, vectors, lower privilege modes, MMU, caches and architectural debug are absent. These cores do not boot Linux.

Documentation and tests

• Documentation index: architecture, contracts and customization.
• Testing: run the functional suite with livt test.
• Change history and license.

Run the functional suite against the resolved dependencies before publishing. FPGA resources and timing depend on the complete composition, parameters and target; validate them for your application.

This package contains reusable source, functional tests and user documentation.