Eccelerators.RiscV

livt.toml

[project]
name = "Eccelerators.RiscV"
version = "0.3.0"
description = "Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt."
authors = ["Denis Vasilík"]
repository = "https://github.com/eccelerators/eccelerators-riscv"
homepage = "https://github.com/eccelerators/eccelerators-riscv"
keywords = ["fpga", "riscv", "rv32i", "processor", "cpu"]
license = "MIT"
path = "src"
outdir = "out"

[project.organization]
name = "Eccelerators GmbH"
website = "https://eccelerators.com"

[publish]
files = ["README.md", "CHANGELOG.md", "LICENSE"]

[tests]
path = "tests"
components = [
    "Rv32FetchBusTest",
    "Rv32LoadStoreBusTest",
    "Rv32BusCoreTest",
    "Rv32BusProtocolTest",
    "RvSystemTest",
    "RvPipelineSystemTest",
    "RvMachineSystemTest",
    "RvUartDeviceTest",
    "RvUartSystemTest",
    "Rv32ZicsrAccessTest",
    "Rv32PipelineZmmulEngineTest",
    "Rv32PipelineDspEngineTest",
    "Rv32PipelineCsrEngineTest",
    "Rv32PipelineTrapEngineTest",
    "Rv32PipelineTimerInterruptTest",
    "Rv32PipelineExternalInterruptTest",

    "Rv32PipelineEngineTest",
    "Rv32PipelineControlTest",
    "Rv32DualReadRegisterBankTest",
    "Rv32DualReadDistributedTest",
    "Rv32InterruptCsrTest",
    "RvExternalInterruptsTest",
    "Rv32ExternalInterruptTest",
    "RvMachineTimerTest",
    "Rv32TimerInterruptTest",
    "Rv32TrapEngineTest",
    "Rv32MachineDecoderTest",
    "Rv32TrapPolicyTest",
    "Rv32MachineCsrsTest",
    "Rv32ZicsrDecoderTest",
    "Rv32CsrEngineTest",
    "Rv32ZmmulDecodeTest",
    "Rv32IterativeMultiplierTest",
    "Rv32DspMultiplierTest",
    "Rv32DspEngineTest",
    "Rv32DspControlTest",
    "Rv32ZmmulEngineTest",
    "Rv32ZmmulControlTest",
    "Rv32SequentialEngineTest",
    "Rv32SequentialControlTest",
    "Rv32RegisterBankTest",
    "Rv32iConstantsTest",
    "Rv32iDecodeTest",
    "Rv32iSemanticsTest",
    "Rv32iPackageApiTest"
]

[dependencies]
"Livt.IO" = "1.8.1"