Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Contracts/IRvDecoder.lvt

namespace Eccelerators.RiscV.Contracts

/**
 * Blocking decode; output control uses RvDecoded. Caller retains original PC,
 * instruction and length (4 for RV32I). All outputs overwritten on every call.
 * Operation numbering belongs to a paired decoder/execution composition.
 */
public interface IRvDecoder
{
	/**
	 * Decodes one instruction, completing before return. Overwrites control and
	 * immediate on every call; control uses RvDecoded, with IsLegal false on rejection.
	 * The exclusive caller retains original PC, instruction bits and length.
	 */
	fn Decode(instruction: uint, control: out uint, immediate: out uint)
}