Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Machine/Rv32TrapOperations.lvt

namespace Eccelerators.RiscV.Machine

/**
 * Machine-return decode and trap-family coverage for explicit compositions.
 */
public class Rv32TrapOperations
{
	// Decoder/controller capability and operation category, distinct from CSR access.
	public const CAPABILITY: uint = 32
	public const RETURN_KIND: uint = 15
	public const MRET_ENCODING: uint = 0x30200073

	// Timer interrupt mask, cause and elaboration capability.
	public const TIMER_MASK: uint = 0x80
	public const TIMER_CAUSE: uint = 0x80000007
	public const TIMER_CAPABILITY: uint = 64

	// External interrupt identity; priority precedes timer delivery.
	public const EXTERNAL_MASK: uint = 0x800
	public const EXTERNAL_CAUSE: uint = 0x8000000b
	public const EXTERNAL_CAPABILITY: uint = 128

	// Writable interrupt-stack bits in the machine-only status register.
	public const STATUS_MIE: uint = 0x08
	public const STATUS_MPIE: uint = 0x80
	public const STATUS_STACK_SHIFT: int = 4
}