Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/Rv32MultiplyOperations.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * Shared Zmmul decode and execution vocabulary; division/remainder are excluded.
 */
public class Rv32MultiplyOperations
{
	// Multiplication family and kind extend the base sequential vocabulary.
	public const CAPABILITY: uint = 8
	public const KIND: uint = 13
	public const RV32I_ZMMUL_CAPABILITIES: uint = Rv32iOperations.RV32I_CAPABILITIES | CAPABILITY

	// Architectural funct3 encodings for all four RV32 multiplication operations.
	public const MUL: uint = 0
	public const MULH: uint = 1
	public const MULHSU: uint = 2
	public const MULHU: uint = 3
	public const OPCODE: uint = 0x33
	public const FUNCT7: uint = 1
}