Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/Rv32NoMultiplier.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * Constant port termination for an RV32I-only composition; owns no arithmetic
 * state. Its engine must disable multiplication dispatch and decoder acceptance.
 */
component Rv32NoMultiplier : IRv32MultiplyPort
{
	// No supported multiplication operations.
	public const CAPABILITIES: uint = 0

	/**
	 * Produces no completion; there is no instruction provider behind this port.
	 */
	process Drive[]()
	{
		ready = 0b0
		result = 0
	}
}