Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/Rv32iIntegerUnit.lvt

namespace Eccelerators.RiscV.Sequential

/**
 * Shared combinational RV32I integer datapath. The owning engine selects operands,
 * samples the result at an execution edge and alone controls architectural commit.
 */
component Rv32iIntegerUnit
{
	// Concrete integer-family coverage; other families belong to the engine/memory path.
	public const CAPABILITIES: uint = Rv32iOperations.INTEGER_CAPABILITY

	// Selected arithmetic inputs and combinational completion.
	public operation: in logic[4]
	public left: in logic[32]
	public right: in logic[32]
	public result: out logic[32]

	/**
	 * Evaluates the shared pure arithmetic semantics with no scheduled call.
	 */
	process Calculate[]()
	{
		result = Rv32iSemantics.Integer(operation as uint, left as uint, right as uint) as logic[32]
	}
}