Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

src/Sequential/Rv32iZmmulDecoder.lvt

namespace Eccelerators.RiscV.Sequential

using Eccelerators.RiscV.Contracts

/**
 * Combinational RV32I plus Zmmul decoder. Base instructions share Rv32iDecode;
 * only the four multiply encodings are added. DIV/REM remain illegal.
 */
component Rv32iZmmulDecoder : IRv32DecodePort
{
	// Concrete decoder coverage, consumed by composition checks.
	public const CAPABILITIES: uint = Rv32MultiplyOperations.RV32I_ZMMUL_CAPABILITIES

	/**
	 * Adds multiplication to the shared control vocabulary without duplicating RV32I.
	 */
	process Decode[]()
	{
		var word = instruction as uint
		var operation = (word >> 12) & 7
		control = Rv32iDecode.Control(word) as logic[32]
		immediate = Rv32iDecode.Immediate(word) as logic[32]

		if ((word & 127) == Rv32MultiplyOperations.OPCODE
			&& (word >> 25) == Rv32MultiplyOperations.FUNCT7
			&& operation <= Rv32MultiplyOperations.MULHU) {
			control = RvDecoded.Pack((Rv32MultiplyOperations.KIND << Rv32iOperations.KIND_SHIFT) | operation,
				(word >> 7) & 31, (word >> 15) & 31, (word >> 20) & 31,
				true, true, true, true) as logic[32]
		}
	}
}