Eccelerators.RiscV

src/System/RvSystem.lvt

namespace Eccelerators.RiscV.System

using Eccelerators.RiscV.Sequential

/**
 * Owns a selected core and borrows the caller's fetch and load/store providers.
 * Devices, routing, provisioning and peripheral pins belong to the caller.
 * All components share a clock/reset domain. This wrapper adds no registers
 * or arbitration. Use RvMachineSystem to expose machine interrupt inputs.
 */
component RvSystem<TCORE : IRv32ControlPort & new(flip IRv32FetchPort, flip IRv32LoadStorePort)> : IRv32ControlPort
{
	// Owned core; execution controls have one writer in Connect.
	core: TCORE

	/**
	 * Creates the core with exclusive access to the two supplied providers.
	 */
	new(fetch: flip IRv32FetchPort, loadStore: flip IRv32LoadStorePort)
	{
		core = new TCORE(fetch, loadStore)
	}

	/**
	 * Pure wiring preserves the core's edge-level control and retirement contract.
	 */
	process Connect[]()
	{
		core.run = run
		core.stepRequest = stepRequest
		core.restartRequest = restartRequest
		stepAck = core.stepAck
		restartAck = core.restartAck
		idle = core.idle
		halted = core.halted
		pc = core.pc
		faultCause = core.faultCause
		faultValue = core.faultValue
		trapped = core.trapped
		trapPc = core.trapPc
		trapCause = core.trapCause
		trapValue = core.trapValue
		retired = core.retired
		retiredPc = core.retiredPc
		retiredInstruction = core.retiredInstruction
		retiredRd = core.retiredRd
		retiredValue = core.retiredValue
	}
}