Livt packages

Eccelerators.RiscV

Version 0.3.0

Composable RV32I and Zmmul processors, machine-mode support, and reusable FPGA system components written in Livt.

Published files (120)

tests/Rv32ZicsrAccessTest.lvt

namespace Eccelerators.RiscV.Tests

using Eccelerators.RiscV.Machine

/**
 * Architectural corner cases for the six CSR forms, independent of engine timing.
 */
@Test
component Rv32ZicsrAccessTest
{
	/**
	 * Writing x0 as the source still writes zero; rd=x0 suppresses only the read.
	 */
	@Test
	fn WriteZeroAndSuppressRead()
	{
		assert Rv32ZicsrAccess.SelectOperand(1, 0x34001073, 0) == 0
		assert !Rv32ZicsrAccess.RequiresRead(1, 0)
		assert Rv32ZicsrAccess.RequiresRead(1, 3)
		assert Rv32ZicsrAccess.RequiresWrite(1, 0x34001073)
		assert !Rv32ZicsrAccess.RequiresRead(5, 0)
		assert Rv32ZicsrAccess.RequiresWrite(5, 0x34005073)
	}

	/**
	 * A nonzero source register containing zero retains write intent for SET/CLEAR.
	 */
	@Test
	fn EncodedSourceControlsWriteIntent()
	{
		assert Rv32ZicsrAccess.RequiresRead(2, 0)
		assert Rv32ZicsrAccess.RequiresRead(3, 0)
		assert !Rv32ZicsrAccess.RequiresWrite(2, 0x34002073)
		assert !Rv32ZicsrAccess.RequiresWrite(3, 0x34003073)
		assert Rv32ZicsrAccess.RequiresWrite(2, 0x3400a073)
		assert Rv32ZicsrAccess.RequiresWrite(3, 0x3400b073)
		assert Rv32ZicsrAccess.SelectOperand(2, 0x3400a073, 0) == 0
		assert Rv32ZicsrAccess.SelectOperand(3, 0x3400b073, 0xffffffff) == 0xffffffff
	}

	/**
	 * Immediate forms select the encoded five-bit value, never register contents.
	 */
	@Test
	fn ImmediateFormsIgnoreRegisterValue()
	{
		assert Rv32ZicsrAccess.SelectOperand(5, 0x340fd073, 0xffffffff) == 31
		assert Rv32ZicsrAccess.SelectOperand(6, 0x3400e073, 0xffffffff) == 1
		assert Rv32ZicsrAccess.SelectOperand(7, 0x34007073, 0xffffffff) == 0
		assert Rv32ZicsrAccess.RequiresRead(6, 0)
		assert Rv32ZicsrAccess.RequiresRead(7, 0)
		assert !Rv32ZicsrAccess.RequiresWrite(6, 0x34006073)
		assert !Rv32ZicsrAccess.RequiresWrite(7, 0x34007073)
		assert Rv32ZicsrAccess.RequiresWrite(6, 0x340fe073)
		assert Rv32ZicsrAccess.RequiresWrite(7, 0x340ff073)
	}
}