Livt packages

Livt.Bus

Version 2.0.1

Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.

Published files (67)

src/axi4lite/Axi4LiteMaster.lvt

namespace Livt.Bus.Axi4Lite

using Livt.Bus

/**
 * Reusable AXI4-Lite transaction master with independent channel handshakes.
 */
component Axi4LiteMaster<AddressWidth: int = 32, DataWidth: int = 32, AllowNonStandardDataWidth: bool = false, CheckAlignment: bool = true> : IAxi4LiteMaster<Logic[AddressWidth], Logic[DataWidth], Logic[BYTE_COUNT]>, IMemoryMappedMaster<Logic[AddressWidth], Logic[DataWidth], Logic[BYTE_COUNT]>
{
	const BYTE_COUNT: int = DataWidth / 8
static assert DataWidth == 32 || DataWidth == 64 || DataWidth == 128, "DataWidth must be 32, 64 or 128"
static assert AddressWidth >= Bits.RequiredFor(DataWidth / 8 - 1) && AddressWidth <= 64, "AddressWidth cannot represent byte lanes or exceeds 64"
static assert DataWidth != 128 || AllowNonStandardDataWidth, "128-bit AXI-Lite-shaped transfers require AllowNonStandardDataWidth=true; they are not standard AXI4-Lite"

	/**
	 * AXI response code for a successful normal access.
	 */
	public const RESPONSE_OKAY: Logic[2] = 0b00

	/**
	 * AXI response code for a successful exclusive access.
	 */
	public const RESPONSE_EXOKAY: Logic[2] = 0b01

	/**
	 * AXI response code for a target-reported slave error.
	 */
	public const RESPONSE_SLVERR: Logic[2] = 0b10

	/**
	 * AXI response code for an address decode error.
	 */
	public const RESPONSE_DECERR: Logic[2] = 0b11

	/**
	 * Byte-enable value selecting all native data lanes.
	 */
	public const ALL_BYTES: Logic[BYTE_COUNT] = ~(0 as Logic[BYTE_COUNT])

	timeoutTicks: uint
	lastReadValue: Logic[DataWidth]
	lastResponse: Logic[2]
	lastTimedOut: bool

	new()
	{
		this.awaddr = 0x00000000
		this.awprot = 0b000
		this.awvalid = 0b0
		this.wdata = 0x00000000
		this.wstrb = 0b0000
		this.wvalid = 0b0
		this.bready = 0b0
		this.araddr = 0x00000000
		this.arprot = 0b000
		this.arvalid = 0b0
		this.rready = 0b0
		this.timeoutTicks = this.context.TicksFor(1ms)
		this.lastReadValue = 0
		this.lastResponse = RESPONSE_OKAY
		this.lastTimedOut = false
	}

	/**
	 * Sets the timeout applied independently to each AXI handshake stage.
	 * The count is exact; zero times out on the first stalled evaluation.
	 */
	override fn SetTimeoutTicks(timeoutTicks: uint)
	{
		this.timeoutTicks = timeoutTicks
	}

	/**
	 * Returns the timeout applied independently to each AXI handshake stage.
	 */
	override fn GetTimeoutTicks() uint
	{
		return timeoutTicks
	}

	/**
	 * Returns the data captured by the most recently completed read.
	 */
	override fn LastReadValue() Logic[DataWidth]
	{
		return lastReadValue
	}

	/**
	 * Returns the AXI response captured by the most recently completed transaction.
	 */
	override fn LastResponse() Logic[2]
	{
		return lastResponse
	}

	/**
	 * Returns true when the most recent transaction timed out.
	 */
	override fn LastTimedOut() bool
	{
		return lastTimedOut
	}

	/**
	 * Performs one AXI4-Lite write using the selected byte lanes.
	 * Returns true after a response handshake; inspect LastResponse for its status.
	 * After a timeout, the call drains the outstanding transaction before returning.
	 */
	override fn TryWrite(address: Logic[AddressWidth], value: Logic[DataWidth], byteEnable: Logic[BYTE_COUNT]) bool
	{
		if (CheckAlignment) {
			assert (address & ((BYTE_COUNT - 1) as Logic[AddressWidth])) == (0 as Logic[AddressWidth])
		}

		var addressAccepted: bool = false
		var dataAccepted: bool = false
		var elapsed: uint = 0
		var successful: bool = false

		state Start {
			lastResponse = RESPONSE_OKAY
			lastTimedOut = false
			addressAccepted = false
			dataAccepted = false
			elapsed = 0
			successful = false
			this.awaddr = address as Logic[AddressWidth]
			this.awprot = 0b000
			this.awvalid = 0b1
			this.wdata = value as Logic[DataWidth]
			this.wstrb = byteEnable
			this.wvalid = 0b1
			this.bready = 0b0
			goto Transfer
		}

		state Transfer {
			if (this.awready == 0b1) {
				addressAccepted = true
				this.awvalid = 0b0
			}

			if (this.wready == 0b1) {
				dataAccepted = true
				this.wvalid = 0b0
			}

			if (addressAccepted && dataAccepted) {
				this.bready = 0b1
				elapsed = 0
				goto Response
			} elif ((elapsed + 1) >= timeoutTicks) {
				lastTimedOut = true
				successful = false
				goto RecoverWriteTransfer
			} else {
				elapsed = elapsed + 1
				goto Transfer
			}
		}

		state Response {
			if (this.bvalid == 0b1) {
				lastResponse = this.bresp
				goto Complete
			} elif ((elapsed + 1) >= timeoutTicks) {
				lastTimedOut = true
				successful = false
				goto RecoverWriteResponse
			} else {
				elapsed = elapsed + 1
				goto Response
			}
		}

		state Complete {
			this.awvalid = 0b0
			this.wvalid = 0b0
			this.bready = 0b0
			lastTimedOut = false
			successful = true
			goto Finish
		}

		state RecoverWriteTransfer {
			if (this.awready == 0b1) {
				addressAccepted = true
				this.awvalid = 0b0
			}

			if (this.wready == 0b1) {
				dataAccepted = true
				this.wvalid = 0b0
			}

			if (addressAccepted && dataAccepted) {
				this.bready = 0b1
				goto RecoverWriteResponse
			} else {
				goto RecoverWriteTransfer
			}
		}

		state RecoverWriteResponse {
			if (this.bvalid == 0b1) {
				this.bready = 0b0
				goto Finish
			} else {
				goto RecoverWriteResponse
			}
		}

		state Finish {}

		return successful
	}

	/**
	 * Performs one AXI4-Lite read and stores its data for LastReadValue.
	 * Returns true after a data handshake; inspect LastResponse for its status.
	 * After a timeout, the call drains the outstanding transaction before returning.
	 */
	override fn TryRead(address: Logic[AddressWidth]) bool
	{
		if (CheckAlignment) {
			assert (address & ((BYTE_COUNT - 1) as Logic[AddressWidth])) == (0 as Logic[AddressWidth])
		}

		var elapsed: uint = 0
		var successful: bool = false

		state Start {
			lastReadValue = 0
			lastResponse = RESPONSE_OKAY
			lastTimedOut = false
			elapsed = 0
			successful = false
			this.araddr = address as Logic[AddressWidth]
			this.arprot = 0b000
			this.arvalid = 0b1
			this.rready = 0b0
			goto Address
		}

		state Address {
			if (this.arready == 0b1) {
				this.arvalid = 0b0
				this.rready = 0b1
				elapsed = 0
				goto Data
			} elif ((elapsed + 1) >= timeoutTicks) {
				lastTimedOut = true
				successful = false
				goto RecoverReadAddress
			} else {
				elapsed = elapsed + 1
				goto Address
			}
		}

		state Data {
			if (this.rvalid == 0b1) {
				lastReadValue = this.rdata as Logic[DataWidth]
				lastResponse = this.rresp
				goto Complete
			} elif ((elapsed + 1) >= timeoutTicks) {
				lastTimedOut = true
				successful = false
				goto RecoverReadData
			} else {
				elapsed = elapsed + 1
				goto Data
			}
		}

		state Complete {
			this.arvalid = 0b0
			this.rready = 0b0
			lastTimedOut = false
			successful = true
			goto Finish
		}

		state RecoverReadAddress {
			if (this.arready == 0b1) {
				this.arvalid = 0b0
				this.rready = 0b1
				goto RecoverReadData
			} else {
				goto RecoverReadAddress
			}
		}

		state RecoverReadData {
			if (this.rvalid == 0b1) {
				this.rready = 0b0
				goto Finish
			} else {
				goto RecoverReadData
			}
		}

		state Finish {}

		return successful
	}

	/**
	 * Performs a normal AXI4-Lite read. AXI4-Lite has no read byte strobes, so
	 * the lane mask is accepted for the common memory-mapped API and ignored.
	 */
	override fn TryReadMasked(address: Logic[AddressWidth], byteEnable: Logic[BYTE_COUNT]) bool
	{
		return TryRead(address)
	}
}