Livt packages
Livt.Bus
Version 2.0.1
Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.
Published files (67)
src/axi4lite/testing/Axi4LiteTestMaster.lvt
namespace Livt.Bus.Axi4Lite.Testing
using Livt.Bus
using Livt.Bus.Axi4Lite
/**
* Assertion-oriented generic master. Native methods issue exactly one bus transfer.
*/
component Axi4LiteTestMaster<AddressWidth: int = 32, DataWidth: int = 32, AllowNonStandardDataWidth: bool = false, CheckAlignment: bool = true> : Axi4LiteMaster<AddressWidth, DataWidth, AllowNonStandardDataWidth, CheckAlignment>, IMemoryMappedBus<Logic[AddressWidth], Logic[DataWidth], Logic[TEST_BYTE_COUNT]>
{
const TEST_BYTE_COUNT: int = DataWidth / 8
override fn WriteWord(address: Logic[AddressWidth], value: Logic[DataWidth])
{
var completed = this.TryWrite(address, value, ~(0 as Logic[TEST_BYTE_COUNT]))
assert completed == true
assert this.LastResponse() == 0b00
}
override fn WriteMaskedWord(address: Logic[AddressWidth], value: Logic[DataWidth], byteEnable: Logic[TEST_BYTE_COUNT])
{
var completed = this.TryWrite(address, value, byteEnable)
assert completed == true
assert this.LastResponse() == 0b00
}
override fn ReadWord(address: Logic[AddressWidth]) Logic[DataWidth]
{
var completed = this.TryRead(address)
assert completed == true
assert this.LastResponse() == 0b00
return this.LastReadValue()
}
override fn VerifyWord(address: Logic[AddressWidth], expected: Logic[DataWidth])
{
var actual = this.ReadWord(address)
assert actual == expected
}
override fn VerifyMaskedWord(address: Logic[AddressWidth], expected: Logic[DataWidth], mask: Logic[DataWidth])
{
var actual = this.ReadWord(address)
assert (actual & mask) == (expected & mask)
}
override fn Write8(address: Logic[AddressWidth], value: byte)
{
var lane = (address & ((TEST_BYTE_COUNT - 1) as Logic[AddressWidth])) as int
var aligned = address & ~((TEST_BYTE_COUNT - 1) as Logic[AddressWidth])
var data = (value as Logic[DataWidth]) << (lane * 8)
var enables = (1 as Logic[TEST_BYTE_COUNT]) << lane
this.WriteMaskedWord(aligned, data, enables)
}
override fn Read8(address: Logic[AddressWidth]) byte
{
var lane = (address & ((TEST_BYTE_COUNT - 1) as Logic[AddressWidth])) as int
var aligned = address & ~((TEST_BYTE_COUNT - 1) as Logic[AddressWidth])
var data = this.ReadWord(aligned)
return (data >> (lane * 8)) as byte
}
}