Livt packages
Livt.Bus
Version 2.0.1
Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.
Published files (67)
src/wishbone/testing/WishboneTestMaster32.lvt
namespace Livt.Bus.Wishbone.Testing
using Livt.Bus
using Livt.Bus.Wishbone
/**
* Assertion-oriented Wishbone Classic master for component and register tests.
*/
component WishboneTestMaster32 : IWishbone32Master, IMemoryMappedBus32
{
/**
* Byte-select value enabling all four data lanes.
*/
public const ALL_BYTES: Logic[4] = 0b1111
/**
* Status returned after a Wishbone acknowledgement.
*/
public const RESPONSE_OKAY: Logic[2] = 0b00
/**
* Status returned after a local Wishbone timeout.
*/
public const RESPONSE_SLVERR: Logic[2] = 0b10
timeoutTicks: uint
lastReadValue: uint
lastResponse: Logic[2]
lastTimedOut: bool
new()
{
this.adr = 0x00000000
this.sel = 0b0000
this.we = 0b0
this.stb = 0b0
this.datin = 0x00000000
this.cyc = 0b0
this.timeoutTicks = this.context.TicksFor(1ms)
this.lastReadValue = 0
this.lastResponse = RESPONSE_OKAY
this.lastTimedOut = false
}
/**
* Sets the maximum ticks to wait for a Wishbone acknowledgement.
* The count is exact; zero times out on the first stalled evaluation.
*/
override fn SetTimeoutTicks(timeoutTicks: uint)
{
this.timeoutTicks = timeoutTicks
}
/**
* Returns the maximum ticks allowed for an acknowledgement.
*/
override fn GetTimeoutTicks() uint
{
return timeoutTicks
}
/**
* Returns the data captured by the most recently acknowledged read.
*/
override fn LastReadValue() uint
{
return lastReadValue
}
/**
* Returns the normalized status of the most recent transfer.
*/
override fn LastResponse() Logic[2]
{
return lastResponse
}
/**
* Returns true when the most recent transfer timed out without acknowledgement.
*/
override fn LastTimedOut() bool
{
return lastTimedOut
}
/**
* Performs one Wishbone Classic write and returns true when ack is received.
*/
private fn ExecuteWrite32(address: uint, value: uint, byteEnable: Logic[4]) bool
{
var elapsed: uint = 0
var successful: bool = false
state Start {
lastResponse = RESPONSE_OKAY
lastTimedOut = false
elapsed = 0
successful = false
this.adr = address as Logic[32]
this.sel = byteEnable
this.we = 0b1
this.datin = value as Logic[32]
this.stb = 0b1
this.cyc = 0b1
goto Transfer
}
state Transfer {
if (this.ack == 0b1) {
successful = true
goto Finish
} elif ((elapsed + 1) >= timeoutTicks) {
lastResponse = RESPONSE_SLVERR
lastTimedOut = true
successful = false
goto Finish
} else {
elapsed = elapsed + 1
goto Transfer
}
}
state Finish {
this.cyc = 0b0
this.stb = 0b0
this.we = 0b0
this.sel = 0b0000
}
return successful
}
/**
* Performs one Wishbone Classic read and returns true when ack is received.
*/
private fn ExecuteRead32(address: uint) bool
{
var elapsed: uint = 0
var successful: bool = false
state Start {
lastReadValue = 0
lastResponse = RESPONSE_OKAY
lastTimedOut = false
elapsed = 0
successful = false
this.adr = address as Logic[32]
this.sel = ALL_BYTES
this.we = 0b0
this.stb = 0b1
this.cyc = 0b1
goto Transfer
}
state Transfer {
if (this.ack == 0b1) {
lastReadValue = this.datout as uint
successful = true
goto Finish
} elif ((elapsed + 1) >= timeoutTicks) {
lastResponse = RESPONSE_SLVERR
lastTimedOut = true
successful = false
goto Finish
} else {
elapsed = elapsed + 1
goto Transfer
}
}
state Finish {
this.cyc = 0b0
this.stb = 0b0
this.sel = 0b0000
}
return successful
}
/**
* Provides the non-asserting write operation inherited by the common API.
*/
override fn TryWrite32(address: uint, value: uint, byteEnable: Logic[4]) bool
{
var successful = this.ExecuteWrite32(address, value, byteEnable)
state Settle {}
return successful
}
/**
* Provides the non-asserting read operation inherited by the common API.
*/
override fn TryRead32(address: uint) bool
{
var successful = this.ExecuteRead32(address)
state Settle {}
return successful
}
/**
* Writes one byte and asserts that the Wishbone transfer is acknowledged.
*/
override fn Write8(address: uint, value: byte)
{
var lane = (address & (3 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var shiftedValue = (value as uint) << shift
var byteEnable: Logic[4] = 0b0001
if (lane == 1) {
byteEnable = 0b0010
} elif (lane == 2) {
byteEnable = 0b0100
} elif (lane == 3) {
byteEnable = 0b1000
}
var completed = this.ExecuteWrite32(alignedAddress, shiftedValue, byteEnable)
assert completed == true
}
/**
* Writes one aligned halfword and asserts that the transfer is acknowledged.
*/
override fn Write16(address: uint, value: Logic[16])
{
assert (address & (1 as uint)) == (0 as uint)
var lane = (address & (2 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var shiftedValue = (value as uint) << shift
var byteEnable: Logic[4] = 0b0011
if (lane == 2) {
byteEnable = 0b1100
}
var completed = this.ExecuteWrite32(alignedAddress, shiftedValue, byteEnable)
assert completed == true
}
/**
* Writes one word and asserts that the transfer is acknowledged.
*/
override fn Write32(address: uint, value: uint)
{
assert (address & (3 as uint)) == (0 as uint)
var completed = this.ExecuteWrite32(address, value, ALL_BYTES)
assert completed == true
}
/**
* Writes selected byte lanes and asserts that the transfer is acknowledged.
*/
override fn WriteMasked32(address: uint, value: uint, byteEnable: Logic[4])
{
assert (address & (3 as uint)) == (0 as uint)
var completed = this.ExecuteWrite32(address, value, byteEnable)
assert completed == true
}
/**
* Reads one byte and asserts that the transfer is acknowledged.
*/
override fn Read8(address: uint) byte
{
var lane = (address & (3 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var completed = this.ExecuteRead32(alignedAddress)
assert completed == true
return (lastReadValue >> shift) as byte
}
/**
* Reads one aligned halfword and asserts that the transfer is acknowledged.
*/
override fn Read16(address: uint) Logic[16]
{
assert (address & (1 as uint)) == (0 as uint)
var lane = (address & (2 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var completed = this.ExecuteRead32(alignedAddress)
assert completed == true
return (lastReadValue >> shift) as Logic[16]
}
/**
* Reads one word and asserts that the transfer is acknowledged.
*/
override fn Read32(address: uint) uint
{
assert (address & (3 as uint)) == (0 as uint)
var completed = this.ExecuteRead32(address)
assert completed == true
return lastReadValue
}
/**
* Reads one byte and asserts that it equals the expected value.
*/
override fn Verify8(address: uint, expected: byte)
{
var lane = (address & (3 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var completed = this.ExecuteRead32(alignedAddress)
assert completed == true
assert ((lastReadValue >> shift) as byte) == expected
}
/**
* Reads one halfword and asserts that it equals the expected value.
*/
override fn Verify16(address: uint, expected: Logic[16])
{
assert (address & (1 as uint)) == (0 as uint)
var lane = (address & (2 as uint)) as int
var shift = lane * 8
var alignedAddress = address & (0xFFFFFFFC as uint)
var completed = this.ExecuteRead32(alignedAddress)
assert completed == true
assert ((lastReadValue >> shift) as Logic[16]) == expected
}
/**
* Reads one word and asserts that it equals the expected value.
*/
override fn Verify32(address: uint, expected: uint)
{
assert (address & (3 as uint)) == (0 as uint)
var completed = this.ExecuteRead32(address)
assert completed == true
assert lastReadValue == expected
}
/**
* Reads one word and compares only bits selected by the mask.
*/
override fn VerifyMasked32(address: uint, expected: uint, mask: uint)
{
assert (address & (3 as uint)) == (0 as uint)
var completed = this.ExecuteRead32(address)
assert completed == true
assert (lastReadValue & mask) == (expected & mask)
}
}