Livt packages
Livt.Bus
Version 2.0.1
Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.
Published files (67)
tests/avalon/AvalonMasterTest.lvt
namespace Livt.Bus.Tests.Avalon
using Livt.Bus.Avalon
using Livt.Bus.Avalon.Testing
@Test
component AvalonMasterTest
{
master: AvalonMaster32
slave: AvalonTestSlave32
new()
{
this.master = new AvalonMaster32()
this.slave = new AvalonTestSlave32(this.master)
}
@Test
fn RunsDelayedMaskedAndResponseTransactions()
{
slave.Clear()
var timeoutTicks = this.context.TicksFor(2us)
master.SetTimeoutTicks(timeoutTicks)
slave.Configure(3 as uint, 0b00)
assert master.TryWrite32(0x08 as uint, 0x11223344 as uint, 0b1111) == true
assert master.TryWrite32(0x08 as uint, 0xAA00CC00 as uint, 0b1010) == true
assert master.TryRead32(0x08 as uint) == true
assert master.LastReadValue() == (0xAA22CC44 as uint)
assert master.LastResponse() == AvalonMaster32.RESPONSE_OKAY
slave.Configure(0 as uint, 0b10)
assert master.TryRead32(0x08 as uint) == true
assert master.LastResponse() == 0b10
assert master.read == 0b0
assert master.write == 0b0
assert master.byteenable == 0b0000
}
@Test
fn ReportsTimeout()
{
master.SetTimeoutTicks(2 as uint)
slave.Configure(20 as uint, 0b00)
assert master.TryWrite32(0x00 as uint, 0x55AA55AA as uint, 0b1111) == false
assert master.LastTimedOut() == true
assert master.write == 0b0
// Recovery holds the timed-out request stable until Avalon accepts it.
slave.Configure(0 as uint, 0b00)
master.SetTimeoutTicks(10 as uint)
assert master.TryRead32(0x00 as uint) == true
assert master.LastReadValue() == (0x55AA55AA as uint)
assert master.LastTimedOut() == false
}
}