Livt packages
Livt.Bus
Version 2.0.1
Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.
Published files (67)
tests/wishbone/WishboneMasterTest.lvt
namespace Livt.Bus.Tests.Wishbone
using Livt.Bus.Wishbone
using Livt.Bus.Wishbone.Testing
@Test
component WishboneMasterTest
{
master: WishboneMaster32
slave: WishboneTestSlave32
new()
{
this.master = new WishboneMaster32()
this.slave = new WishboneTestSlave32(this.master)
}
@Test
fn RunsDelayedAndMaskedTransactions()
{
slave.Clear()
var timeoutTicks = this.context.TicksFor(2us)
master.SetTimeoutTicks(timeoutTicks)
slave.ConfigureAckDelay(3 as uint)
assert master.TryWrite32(0x0C as uint, 0x12345678 as uint, 0b1111) == true
assert master.TryWrite32(0x0C as uint, 0xAA00CC00 as uint, 0b1010) == true
assert master.TryRead32(0x0C as uint) == true
assert master.LastReadValue() == (0xAA34CC78 as uint)
assert master.LastTimedOut() == false
assert master.cyc == 0b0
assert master.stb == 0b0
assert master.we == 0b0
assert master.sel == 0b0000
}
@Test
fn ReportsTimeout()
{
master.SetTimeoutTicks(2 as uint)
slave.ConfigureAckDelay(20 as uint)
assert master.TryWrite32(0x00 as uint, 0x55AA55AA as uint, 0b1111) == false
assert master.LastTimedOut() == true
assert master.LastResponse() == WishboneMaster32.RESPONSE_SLVERR
assert master.cyc == 0b0
assert master.stb == 0b0
// The target observes cancellation and is immediately reusable.
slave.ConfigureAckDelay(0 as uint)
master.SetTimeoutTicks(10 as uint)
assert master.TryRead32(0x00 as uint) == true
assert master.LastReadValue() == (0x00000000 as uint)
assert master.LastResponse() == WishboneMaster32.RESPONSE_OKAY
}
}