Livt packages

Livt.Bus

Version 2.0.1

Configurable Avalon, AXI4-Lite, and Wishbone memory-mapped masters, interfaces, bridges, and test components.

Published files (67)

tests/wishbone/WishboneTestMasterTest.lvt

namespace Livt.Bus.Tests.Wishbone

using Livt.Bus.Wishbone.Testing

@Test
component WishboneTestMasterTest
{
	master: WishboneTestMaster32
	slave: WishboneTestSlave32

	new()
	{
		this.master = new WishboneTestMaster32()
		this.slave = new WishboneTestSlave32(this.master)
	}

	@Test
	fn ExercisesVerificationApi()
	{
		slave.Clear()
		var timeoutTicks = this.context.TicksFor(2us)
		master.SetTimeoutTicks(timeoutTicks)
		assert master.GetTimeoutTicks() == timeoutTicks
		slave.ConfigureAckDelay(2 as uint)

		master.Write32(0x08 as uint, 0x11223344 as uint)
		master.Verify32(0x08 as uint, 0x11223344 as uint)
		master.WriteMasked32(0x08 as uint, 0xAA00CC00 as uint, 0b1010)
		master.VerifyMasked32(0x08 as uint, 0xAA22CC44 as uint, 0xFFFFFFFF as uint)

		master.Write8(0x09 as uint, 0x5A as byte)
		master.Verify8(0x09 as uint, 0x5A as byte)
		assert master.Read8(0x09 as uint) == (0x5A as byte)

		master.Write16(0x0A as uint, 0xCAFE as Logic[16])
		master.Verify16(0x0A as uint, 0xCAFE as Logic[16])
		assert master.Read16(0x0A as uint) == (0xCAFE as Logic[16])
		assert master.Read32(0x08 as uint) == (0xCAFE5A44 as uint)
	}

	@Test
	fn ExposesNonAssertingTimeoutApi()
	{
		master.SetTimeoutTicks(2 as uint)
		slave.ConfigureAckDelay(20 as uint)
		assert master.TryRead32(0x00 as uint) == false
		assert master.LastTimedOut() == true
		assert master.LastResponse() == WishboneTestMaster32.RESPONSE_SLVERR
		slave.ConfigureAckDelay(0 as uint)
		master.SetTimeoutTicks(10 as uint)
		assert master.TryRead32(0x00 as uint) == true
		assert master.LastResponse() == WishboneTestMaster32.RESPONSE_OKAY
		assert master.LastTimedOut() == false
	}
}