Livt.Collections

src/fifo/AsyncFifoArray.lvt

namespace Livt.Collections

/**
 * Reset-free array with one clocked write port and an independent read tap.
 * Inherits the FIFO's write context. The FIFO owns read-domain registration.
 * STYLE requests a resource category without changing the read contract.
 * Auto does not force registers; Block is only a hint, and asynchronous reads
 * may prevent block-memory inference unless synthesis merges the read register.
 */
component AsyncFifoArray<T, CAPACITY: int = 256,
	STYLE: MemoryStyle = MemoryStyle.Auto>
	: IFifoStorage<T, FifoStorageGeometry<CAPACITY>>
{
	static assert CAPACITY >= 2, "FIFO storage capacity must be at least two"

	// Single-owner payload cells, never reset or initialized as an array.
	@Memory(Style = STYLE)
	@UninitializedStorage
	cells: T[CAPACITY]

	// Live write inputs; storage commits on the FIFO's accepting edge.
	writeEnableWire: bool
	writeAddressWire: uint
	writeDataWire: T

	/**
	 * Binds write pins and exposes the read tap without scheduled field accessors.
	 */
	process Connect[]()
	{
		this.readData = cells[this.readAddress]
		this.writeEnableWire = this.writeEnable
		this.writeAddressWire = this.writeAddress
		this.writeDataWire = this.writeData
	}

	/**
	 * Commits at most one payload per write edge, retaining cells on reset.
	 */
	process WritePort()
	{
		state Tick {
			if (writeEnableWire && context.rst == 0b0) {
				this.cells[writeAddressWire] = writeDataWire
			}

			goto Tick
		}
	}
}