Livt packages

Livt.IO

Version 1.8.1

Memory, UART, I2C, SPI, and Ethernet input/output components for Livt hardware designs.

Published files (126)

tests/uart/UartSynthesisConfigurationTest.lvt

namespace Livt.IO.Tests

using Livt.IO

/**
 * Keeps the default 64/64, 8-N-1, 115200-baud buffered configurations available
 * to the reproducible cross-FPGA synthesis benchmark.
 */
@Test
@Context(ClockFrequency = 100MHz)
component UartSynthesisConfigurationTest
{
	// Shared fixture instances, signals, and observation state.
	buffered: BufferedUart
	flowControlled: RtsCtsBufferedUart

	// Shared fixture instances, signals, and observation state.
	bufferedLine: logic = 0b1
	flowControlledLine: logic = 0b1
	ctsN: logic = 0b0
	rtsN: logic

	/**
	 * Creates the shared fixture instances (BufferedUart, RtsCtsBufferedUart). Tests
	 * initialize the state required by their scenario.
	 */
	new()
	{
		this.buffered = new BufferedUart(this.bufferedLine, this.bufferedLine)
		this.flowControlled = new RtsCtsBufferedUart(
			this.flowControlledLine,
			this.flowControlledLine,
			this.ctsN,
			this.rtsN
		)
	}

	/**
	 * Checks the default capacities case.
	 */
	@Test
	fn TestDefaultCapacities()
	{
		assert this.buffered.GetTransmitSpace() == 64
		assert this.flowControlled.GetTransmitSpace() == 64
	}
}